Eric Fossum
Senior Member
Mike, it looked to me like RS was not biased as a cascode device but perhaps that was your intention all along. On the other hand, the CS source voltage will be hard to keep quiet in an array configuration and I believe that voltage level is quite important.Eric,hi Mike,Hello,
As a disclaimer, I'm not a sensor chip designer (although I do have a related patent on electron leakage reduction for night vision sensors), I'm an analog/RF chip/system designer. So please take my comments lightly and don't rip me to shreds :-|
With the pixel Source Follower (SF) as the first amplifier in the sensor voltage channel chain, this seems as a major source of electronic induced noise (like the LNA in RF receiver systems) that can't be reduced with post gain (sets the lower overall system "noise figure"). Since the SF has less than unity voltage gain, the system input referred noise is rather high, higher than if it were a Common Source (CS) which has potentially higher than unity voltage gain.
I've captured a screen shot of the Aptina mentioned White Paper, shown below. The left is Figure 5 from the white paper and the right side is a modification shown in orange. The SF amplifier is replaced with a CS amplifier by using a PMOS instead of a NMOS device and the source is returned to the RS line which I assume is a higher voltage when active than supply Vaa_PIX.
The voltage output Vout is inverted since the SF is a follower and the CS is an inverting amplifier. Vout can swing a higher peak to peak voltage than the SF which may be beneficial with less post amplification required and since the gain magnitude may be greater than unity the overall system input referred noise could be lower as well. No additional control, power nor signal lines are required either.
Anyway, this was just a thought. Please let me know what you think.
Best,
Pixel Level Common Source Amplifier Concept shown in Orange
Thank you for sharing your CS idea. Generally a CS amp will work but any improvement is offset by a few factors. (1) CS-drain is about equal to Vout so you get gate-drain Miller capacitance (2) current fluctuations in CS (origin of 1/f noise) are also amplified in this configuration and (3) implementing PMOS in the pixel is not convenient due to layout rules. It is a common suggestion (usually NMOS CS) and some people have made it work, although not really with any compelling advantage. Thus it has not made it to widespread use. Actually, I am not sure anyone has tried PMOS CS - perhaps the reduced intrinsic 1/f noise will help.
Anyway, try simulating this and see what you get!
Eric
Thanks, very familiar with 1/f noise and the Miller effects, always try and use Cascode stages to help when possible.
If the output of the PMOS CS amplifier was a current rather than voltage, which would be routed thru the NMOS RS device, with a variable effective load a variable voltage gain referenced to the pixel could be achieved. A common use low noise Cascode Stage could make the impedance as seen from the PMOS drain very low thus minimizing the Miller effect and isolating a variable transconductance stage for variable voltage gain control.
Yes, I probably should try and get this simulated sometime.
Thanks for the reply and notes.
Best,
--
~Mike~
Variable gain for one pixel is nice -- the problem often occurs when you try to make an entire array of millions of pixels behave exactly the same way without FPN or PRNU.
I had one PhD student who probably spent a month trying to make a CS amplifier work and could not get better input-referred noise than by making the input cap to the SF as small as possible.
If you are successful in your simulations, please write me at my Dartmouth email address, which is easy to find, for further discussions. Maybe you have already done the simulations since it is a relatively easy circuit.
BTW, current mode readout has also been explored over the years. So far no real success. Buffer-followers seems to work the best, so far...
