I really don't want to get back into the same pretty pointless exchange that want on in the last thread, but I think this post is a pretty one-sided representation of the discussion. I'm just going to annotate it to put my side and then be done.
DSPographer wrote:
The thread also took a side track in a discussion about normalizing read noise per sensor area when bobn2 posted the following scaling law:
"I think that input referred read noise, that is expressed in 'electrons' is fundamentally affected by the 'gain' (charge/voltage factor) which in turn is controlled by the capacitance of the SF and floating diffusion. That in turn is controlled by the area. So, if we want to isolate the effect of one variable (there are of course many) then we need to look at how things change if you change just that variable. So if you use the same process, same design and simply do a uniform geometrical scale than the capacitance of the read node will fall proportional to area, and so will the read noise."
And this is an effect that no-one has mounted any argument against. So, we have a clear effect that if you make the SF/FD smaller, the conversion gain will rise and the input referred noise for a given voltage noise. The question is, if you change the size of the SF/FD, does the voltage noise change and if so, does it change by enough to cancel out this effect.
He then added this caveat:
"Now of course, there are many more variables, and designers don't make pixels smaller simply by scaling, and in some cases are constrained by process limits"
While designers do not simply make pixels smaller by scaling, it seems a fair assumption that smaller SF/FD will be used as pixels shrink. The 'uniform scaling' model simply models that. We don't know in practice whether instead of shrinking the active parts of the pixel, some designers are willing to sacrifice fill factor, or a bit of both. Nonetheless, we might expect smaller pixels to result in smaller components and thus be subject to the effect above, to some degree. I have also added the caveat that there are noises which will increase as the transistor is reduced in size. Leaving that out allows my position to be characterised as saying that the CG effect is the only one in operation. That is a mischaracterisation of what I have said.
But he then goes on to imply this is the reason for the improvements in read noise:
"(though for those that claim that they must always use design rules on process limits, it's notable that Canon made a three-fold reduction in pixel area, while reducing read noise (co-incidentally, three fold) and increasing QE, using the same 500nm process)."
It's asking the question of people who believe component size must always be driven by process limits. Canon has shrunk pixels by a factor of three, while increasing QE and using the same process limits. I think its hard to conceive how they did that without shrinking components, in which case the original designs cannot have been close to process limits.
Now bobn2 and I had discussed this before. The issue was not that we disagreed about what happens for a given scaling rule, it was which scaling rule was relevant when discussing how read noise varies with pixel size. He felt the law above was most relevant; and I felt that for a given generation designers would be most likely to use a minimum effective gate length for the critical SF transistor based on process capability (note that improvements in effective gate length are still possible within a single process as it matures), and vary the gate width to achieve the FD capacitance needed for the desired full well capacity. Using arguments based on transistor thermal noise bob's model suggests that read noise should scale by pixel area, and my model suggests read noise could be independent of area.
See above.
Which is right? It turns out that it seems that neither model is very relevant. First, the assumption that simple thermal noise dominates read noise is not valid; and secondly, the most important factors in pixel read noise may not be included in our simplistic models.
However, the conversion gain effect must operate. The question is not whether it has an effect, but what other effects confound it, and to what end effect.
We are fortunate that someone actually involved in reducing read noise in image sensors, Eric Fossum, contributed to the thread. He listed the factors involved in reducing read noise:
"I think I have written this before but the read noise of the pixel in the case of correlated double sampling (CDS), depends on size of the main readout transistor. Smaller = noisier, in general. The noise is often limited by random-telegraph signal (RTS) noise which is thought to be a major contributor to 1/f noise. When possible, we make the main readout transistor as large as possible without compromising pixel fill factor.
The real question here is whether eric is referring to input referred or voltage noise. This isn't clear. I think the above must be true in terms of voltage noise, smaller transistors will be noiser. The question is still whether or not it frustrates
So, based on this we would expect an increase in read noise as we shrink pixels. Image sensor technologists have tried to reverse this by several techniques.
1. BSI - one benefit of BSI is more room for the readout electronics and that key transistor.
Clearly, when we compare DSLR sensors BSI is not an effect, so we can ignore that as and explanation for the noise reduction in the sensors.
2. More attention to reducing the defects that contribute to RTS and hence reduce the noise of the transistor, or by burying the channel so surface defects don't contribute.
Certainly.
3. Increasing the conversion gain of the output node (volts/electron = 1/capacitance) so the input-referred noise appears to drop, even if the voltage noise increases. This is the standard EE approach - add gain as early as possible in the signal chain. Increasing the conversion gain is possible because FWC has dropped so there is often less charge to accomodate on the output node. Smaller technology also helps make the output node smaller and have less capacitance.
This is exactly the effect that I have posited above. (my emboldening)
4. Improving CDS, for example by digital CDS, so that any residual correlated noise is further reduced.
Improved CDS will help reset noise.
Probably there are one or two other things I have forgotten for the moment. The bottom line is that the result of these measures is a net DECREASE in read noise down to the 1-5 e- rms level. It has been a lot of hard work to reduce the read noise. (and another big effort in increasing FWC which is more or less a separate endeavor except for conversion gain). But if one were to plot read noise as a function of pixel size, as you guys like to do, you will see the outcome of this war on read noise. But, don't get fooled into thinking read noise seems to be scaling with pixel area due to any fundamental or natural technological reason."
Dr. Fossum also summarized how the reduction of read noise relates to a uniform pixel shrink:
"So, the recap the recap, the downward read noise trend is the result of hard work and new innovation, and NOT the natural result of scaling everything with area. You cannot just shrink the pixel this way. If it was, life would be a lot easier. As I have said several times, creating a predictive trend model is fine, but does not reflect cause and effect."
Which is arguing against something that I never said. I have never said that smaller pixels are designed simply by scaling bigger ones, simply that as an abstraction of the process of shrinking pixels, scaling is the most sensible one, because it models the fact that as pixels reduce in size the internal components of a pixel will be reduced in size, which they will be, if fill factor is not to suffer. Note that the capacitance reduction effect, and resultant rise in CG is definitely one of the factors which Eric says mitigate the rise and result in a 'net DECREASE in read noise' (his words, not mine). I hope at least I can continue to say that the rise in CG due to the reduction in component size is one of the factors which has contributed to the decrease, which is all my case amounts to, and which Eric confirms.
PS: A scaling rule based on 1/f noise instead of thermal noise was also posted to the thread. I personally doubt that this is very useful for predicting how pixel noise would change as a pixel is shrunk. The reason is that the formula includes a process dependent factor. My understanding is that factor could greatly change as a new process is created to allow smaller pixels.
If we try to isolate the effect of one factor, we assume all other factors remain constant. that is the usual engineering practice. The process dependent constant (and there is another different one in the RTS equations) simply would give process dependent constants in any expression derived for the effects of scaling. That's not a bad thing. And the concept of scaling is fundamental to LSI design, that is why lambda based design rules are adopted across the industry.