Read Noise from DXOmark "Full SNR" data . 2

Started Oct 31, 2013 | Discussions
Mikael Risedal
Mikael Risedal Veteran Member • Posts: 4,644
Read Noise from DXOmark "Full SNR" data . 2

Conclusion?

Now when  the storm seems to have subsided, did you come to any conclusion ?

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DSPographer Senior Member • Posts: 2,483
Re: Read Noise from DXOmark "Full SNR" data . 2

First of all the original point of the thread was I provided a way to get read noise, full well capacity, and PRNU from DXOmark's "Full SNR" plot data:

http://www.dpreview.com/forums/post/52400156

Now these plots have already been parameterized by these 3 factors by DXO, so when you correctly fit any three points on the plot, you can generate a curve that goes *exactly* through all points on the plot (to double precision accuracy) using this noise model:

noise^2 = n^2 + m*x + G * m^2 * x^2

x : fraction of saturation count
G : pixel gain variance (PRNU^2)
m : saturation count
n : read noise

Now bobn2 had previously created the sensorgen.info website to list these parameter values, and more, as derived from the DXOmark plots. So why did I provide this alternative method?

Unfortunately, while very generous of bobn2, the sensorgen data has a few issues:

First of all the fit he gets is usually slightly different than the exact fit. This is odd, because that means his fit doesn't go through the points on the plot. This error, while odd, seems to usually be small.

More seriously, sometimes his plots differ wildly in the parameter values from the parameters that would generate DXO's plot. For instance, the Nikon D800 at ISO 100 is listed with a read noise of 2.7 e- when the correct vale is 4.55 e-, and the Canon 60D at ISO 3200 is listed with a read noise of 4.1 e- when it should be 2.66 e-. These values are so far off that I wonder if something went wrong in his script for pulling down or parsing the data.

Another issue is that the DXO fit itself yields erratic values for read noise when the full well count is below 1000 e-. (This can be seen by observing the trend in how the parameters change as the ISO increases for all cameras.) Since the sensorgen table which summarizes the minimum read noise for the cameras includes these erratic values, the table is not useful.

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DSPographer Senior Member • Posts: 2,483
Re: Read Noise vs Pixel Pitch

The thread also took a side track in a discussion about normalizing read noise per sensor area when bobn2 posted the following scaling law:

"I think that input referred read noise, that is expressed in 'electrons' is fundamentally affected by the 'gain' (charge/voltage factor) which in turn is controlled by the capacitance of the SF and floating diffusion. That in turn is controlled by the area. So, if we want to isolate the effect of one variable (there are of course many) then we need to look at how things change if you change just that variable. So if you use the same process, same design and simply do a uniform geometrical scale than the capacitance of the read node will fall proportional to area, and so will the read noise."

He then added this caveat:
"Now of course, there are many more variables, and designers don't make pixels smaller simply by scaling, and in some cases are constrained by process limits"

But he then goes on to imply this is the reason for the improvements in read noise:
"(though for those that claim that they must always use design rules on process limits, it's notable that Canon made a three-fold reduction in pixel area, while reducing read noise (co-incidentally, three fold) and increasing QE, using the same 500nm process)."

Now bobn2 and I had discussed this before. The issue was not that we disagreed about what happens for a given scaling rule, it was which scaling rule was relevant when discussing how read noise varies with pixel size. He felt the law above was most relevant; and I felt that for a given generation designers would be most likely to use a minimum effective gate length for the critical SF transistor based on process capability (note that improvements in effective gate length are still possible within a single process as it matures), and vary the gate width to achieve the FD capacitance needed for the desired full well capacity. Using arguments based on transistor thermal noise bob's model suggests that read noise should scale by pixel area, and my model suggests read noise could be independent of area.

Which is right? It turns out that it seems that neither model is very relevant. First, the assumption that simple thermal noise dominates read noise is not valid; and secondly, the most important factors in pixel read noise may not be included in our simplistic models.

We are fortunate that someone actually involved in reducing read noise in image sensors, Eric Fossum, contributed to the thread. He listed the factors involved in reducing read noise:

"I think I have written this before but the read noise of the pixel in the case of correlated double sampling (CDS), depends on size of the main readout transistor. Smaller = noisier, in general. The noise is often limited by random-telegraph signal (RTS) noise which is thought to be a major contributor to 1/f noise. When possible, we make the main readout transistor as large as possible without compromising pixel fill factor.

So, based on this we would expect an increase in read noise as we shrink pixels. Image sensor technologists have tried to reverse this by several techniques.

1. BSI - one benefit of BSI is more room for the readout electronics and that key transistor.

2. More attention to reducing the defects that contribute to RTS and hence reduce the noise of the transistor, or by burying the channel so surface defects don't contribute.

3. Increasing the conversion gain of the output node (volts/electron = 1/capacitance) so the input-referred noise appears to drop, even if the voltage noise increases. This is the standard EE approach - add gain as early as possible in the signal chain. Increasing the conversion gain is possible because FWC has dropped so there is often less charge to accomodate on the output node. Smaller technology also helps make the output node smaller and have less capacitance.

4. Improving CDS, for example by digital CDS, so that any residual correlated noise is further reduced.

Probably there are one or two other things I have forgotten for the moment. The bottom line is that the result of these measures is a net DECREASE in read noise down to the 1-5 e- rms level. It has been a lot of hard work to reduce the read noise. (and another big effort in increasing FWC which is more or less a separate endeavor except for conversion gain). But if one were to plot read noise as a function of pixel size, as you guys like to do, you will see the outcome of this war on read noise. But, don't get fooled into thinking read noise seems to be scaling with pixel area due to any fundamental or natural technological reason."

Dr. Fossum also summarized how the reduction of read noise relates to a uniform pixel shrink:

"So, the recap the recap, the downward read noise trend is the result of hard work and new innovation, and NOT the natural result of scaling everything with area. You cannot just shrink the pixel this way. If it was, life would be a lot easier. As I have said several times, creating a predictive trend model is fine, but does not reflect cause and effect."

PS: A scaling rule based on 1/f noise instead of thermal noise was also posted to the thread. I personally doubt that this is very useful for predicting how pixel noise would change as a pixel is shrunk. The reason is that the formula includes a process dependent factor. My understanding is that factor could greatly change as a new process is created to allow smaller pixels.

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The_Suede Contributing Member • Posts: 652
Unrelated question

Shouldn't (hm) DR really be defined with the total noise sum, in stead of "just" read noise"...? I.e DR = the point where SNR=1, not the point where RN = signal?

I mean - The full signal is the sum of the parts. To get SNR=1 you add RN and PN before comparing with signal. The definition of "usable signal" is better correlated with SNR than with read noise, IMO.

For your value of 4.55e- at ISO100 for the D800, FWC of 48,800, I get a technical DR of 13.39. DxO (from which the figures originated) state 13.23.

Are they using SNR=1?

48,800 / 2^13.23 = 5.08e- at their DR point >>> 2.25 in PN

sqrt(5.08 + 4.55^2) = 5.08

Guess I answered my own question there...

DSPographer Senior Member • Posts: 2,483
Re: Read Noise from DXOmark "Full SNR" data . 2

Both pixel size and pixel noise have tended to decrease with time. Now bobn2 has suggested this is a cause and effect relationship resulting from his scaling law. To help disentangle the relationship of pixel noise versus time and pixel size I posted a couple of observational examples to isolate the two effects.

First I posted the 1DsII versus the 1DX because they have nearly the same pixel size but differ in when they were introduced (I could also have used Canon's new yet relatively inexpensive 6D instead of the 1DX since its read noise is just as low: but its pixel size wasn't as close to the 1DsII pixel's)

Just check an early large pixel sensor vs a recent one: like Canon's 1DsII (with 7 micron pixels) vs. the 1DX (with 6.9 micron pixels):

Next I plotted the minimum read noise vs pixel size of all of Canon's latest cameras that are in the DXOmark database:

I plot the read noise at the highest ISO with a full well capacity of at least 1000 e- because the DXOmark data is unreliable when the full well count is less than that. I also include the trend lines for noise scaling by pixel pitch (in green) and by pixel area (in red) for comparison. Here is the plot:

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Jack Hogan Veteran Member • Posts: 7,989
Re: Unrelated question

The_Suede wrote:

Shouldn't (hm) DR really be defined with the total noise sum, in stead of "just" read noise"...? I.e DR = the point where SNR=1, not the point where RN = signal?

Yes, although the difference is often immaterial.

I mean - The full signal is the sum of the parts. To get SNR=1 you add RN and PN before comparing with signal. The definition of "usable signal" is better correlated with SNR than with read noise, IMO.

For your value of 4.55e- at ISO100 for the D800, FWC of 48,800, I get a technical DR of 13.39. DxO (from which the figures originated) state 13.23.

Are they using SNR=1?

Yes

48,800 / 2^13.23 = 5.08e- at their DR point >>> 2.25 in PN

sqrt(5.08 + 4.55^2) = 5.08

Guess I answered my own question there...

cpw Regular Member • Posts: 313
Re: Unrelated question

Jack Hogan wrote:

The_Suede wrote:

Shouldn't (hm) DR really be defined with the total noise sum, in stead of "just" read noise"...? I.e DR = the point where SNR=1, not the point where RN = signal?

Yes, although the difference is often immaterial.

I mean - The full signal is the sum of the parts. To get SNR=1 you add RN and PN before comparing with signal. The definition of "usable signal" is better correlated with SNR than with read noise, IMO.

For your value of 4.55e- at ISO100 for the D800, FWC of 48,800, I get a technical DR of 13.39. DxO (from which the figures originated) state 13.23.

Are they using SNR=1?

Yes

48,800 / 2^13.23 = 5.08e- at their DR point >>> 2.25 in PN

sqrt(5.08 + 4.55^2) = 5.08

Guess I answered my own question there...

Hey guys,

Yes, I'll repeat what you have above a little more formally, there's 2 defs. of engineering DR here:

1)  the one I'm used to, DR = FW/Nr

2) Dxomarks DR(Dxo) = FW/S*

where S* = signal at which SNR = 1.  So S* = sqrt(S* + Nr^2), and when you solve for S*, you get S* = sqrt(Nr^2 + (1/2)^2) + (1/2).  S* will always be about 0.5 e higher than Nr, when camera makers are starting to get down lower in Nr, it will matter a little more.

And so it's totally reasonable to get a measured DR slightly > DR(Dxo).

Chris

bobn2
bobn2 Forum Pro • Posts: 69,811
Re: Read Noise vs Pixel Pitch

I really don't want to get back into the same pretty pointless exchange that want on in the last thread, but I think this post is a pretty one-sided representation of the discussion. I'm just going to annotate it to put my side and then be done.

DSPographer wrote:

The thread also took a side track in a discussion about normalizing read noise per sensor area when bobn2 posted the following scaling law:

"I think that input referred read noise, that is expressed in 'electrons' is fundamentally affected by the 'gain' (charge/voltage factor) which in turn is controlled by the capacitance of the SF and floating diffusion. That in turn is controlled by the area. So, if we want to isolate the effect of one variable (there are of course many) then we need to look at how things change if you change just that variable. So if you use the same process, same design and simply do a uniform geometrical scale than the capacitance of the read node will fall proportional to area, and so will the read noise."

And this is an effect that no-one has mounted any argument against. So, we have a clear effect that if you make the SF/FD smaller, the conversion gain will rise and the input referred noise for a given voltage noise. The question is, if you change the size of the SF/FD, does the voltage noise change and if so, does it change by enough to cancel out this effect.

He then added this caveat:
"Now of course, there are many more variables, and designers don't make pixels smaller simply by scaling, and in some cases are constrained by process limits"

While designers do not simply make pixels smaller by scaling, it seems a fair assumption that smaller SF/FD will be used as pixels shrink. The 'uniform scaling' model simply models that. We don't know in practice whether instead of shrinking the active parts of the pixel, some designers are willing to sacrifice fill factor, or a bit of both. Nonetheless, we might expect smaller pixels to result in smaller components and thus be subject to the effect above, to some degree. I have also added the caveat that there are noises which will increase as the transistor is reduced in size. Leaving that out allows my position to be characterised as saying that the CG effect is the only one in operation. That is a mischaracterisation of what I have said.

But he then goes on to imply this is the reason for the improvements in read noise:
"(though for those that claim that they must always use design rules on process limits, it's notable that Canon made a three-fold reduction in pixel area, while reducing read noise (co-incidentally, three fold) and increasing QE, using the same 500nm process)."

It's asking the question of people who believe component size must always be driven by process limits. Canon has shrunk pixels by a factor of three, while increasing QE and using the same process limits. I think its hard to conceive how they did that without shrinking components, in which case the original designs cannot have been close to process limits.

Now bobn2 and I had discussed this before. The issue was not that we disagreed about what happens for a given scaling rule, it was which scaling rule was relevant when discussing how read noise varies with pixel size. He felt the law above was most relevant; and I felt that for a given generation designers would be most likely to use a minimum effective gate length for the critical SF transistor based on process capability (note that improvements in effective gate length are still possible within a single process as it matures), and vary the gate width to achieve the FD capacitance needed for the desired full well capacity. Using arguments based on transistor thermal noise bob's model suggests that read noise should scale by pixel area, and my model suggests read noise could be independent of area.

See above.

Which is right? It turns out that it seems that neither model is very relevant. First, the assumption that simple thermal noise dominates read noise is not valid; and secondly, the most important factors in pixel read noise may not be included in our simplistic models.

However, the conversion gain effect must operate. The question is not whether it has an effect, but what other effects confound it, and to what end effect.

We are fortunate that someone actually involved in reducing read noise in image sensors, Eric Fossum, contributed to the thread. He listed the factors involved in reducing read noise:

"I think I have written this before but the read noise of the pixel in the case of correlated double sampling (CDS), depends on size of the main readout transistor. Smaller = noisier, in general. The noise is often limited by random-telegraph signal (RTS) noise which is thought to be a major contributor to 1/f noise. When possible, we make the main readout transistor as large as possible without compromising pixel fill factor.

The real question here is whether eric is referring to input referred or voltage noise. This isn't clear. I think the above must be true in terms of voltage noise, smaller transistors will be noiser. The question is still whether or not it frustrates

So, based on this we would expect an increase in read noise as we shrink pixels. Image sensor technologists have tried to reverse this by several techniques.

1. BSI - one benefit of BSI is more room for the readout electronics and that key transistor.

Clearly, when we compare DSLR sensors BSI is not an effect, so we can ignore that as and explanation for the noise reduction in the sensors.

2. More attention to reducing the defects that contribute to RTS and hence reduce the noise of the transistor, or by burying the channel so surface defects don't contribute.

Certainly.

3. Increasing the conversion gain of the output node (volts/electron = 1/capacitance) so the input-referred noise appears to drop, even if the voltage noise increases. This is the standard EE approach - add gain as early as possible in the signal chain. Increasing the conversion gain is possible because FWC has dropped so there is often less charge to accomodate on the output node. Smaller technology also helps make the output node smaller and have less capacitance.

This is exactly the effect that I have posited above. (my emboldening)

4. Improving CDS, for example by digital CDS, so that any residual correlated noise is further reduced.

Improved CDS will help reset noise.

Probably there are one or two other things I have forgotten for the moment. The bottom line is that the result of these measures is a net DECREASE in read noise down to the 1-5 e- rms level. It has been a lot of hard work to reduce the read noise. (and another big effort in increasing FWC which is more or less a separate endeavor except for conversion gain). But if one were to plot read noise as a function of pixel size, as you guys like to do, you will see the outcome of this war on read noise. But, don't get fooled into thinking read noise seems to be scaling with pixel area due to any fundamental or natural technological reason."

Dr. Fossum also summarized how the reduction of read noise relates to a uniform pixel shrink:

"So, the recap the recap, the downward read noise trend is the result of hard work and new innovation, and NOT the natural result of scaling everything with area. You cannot just shrink the pixel this way. If it was, life would be a lot easier. As I have said several times, creating a predictive trend model is fine, but does not reflect cause and effect."

Which is arguing against something that I never said. I have never said that smaller pixels are designed simply by scaling bigger ones, simply that as an abstraction of the process of shrinking pixels, scaling is the most sensible one, because it models the fact that as pixels reduce in size the internal components of a pixel will be reduced in size, which they will be, if fill factor is not to suffer. Note that the capacitance reduction effect, and resultant rise in CG is definitely one of the factors which Eric says mitigate the rise and result in a 'net DECREASE in read noise' (his words, not mine). I hope at least I can continue to say that the rise in CG due to the reduction in component size is one of the factors which has contributed to the decrease, which is all my case amounts to, and which Eric confirms.

PS: A scaling rule based on 1/f noise instead of thermal noise was also posted to the thread. I personally doubt that this is very useful for predicting how pixel noise would change as a pixel is shrunk. The reason is that the formula includes a process dependent factor. My understanding is that factor could greatly change as a new process is created to allow smaller pixels.

If we try to isolate the effect of one factor, we assume all other factors remain constant. that is the usual engineering practice. The process dependent constant (and there is another different one in the RTS equations) simply would give process dependent constants in any expression derived for the effects of scaling. That's not a bad thing. And the concept of scaling is fundamental to LSI design, that is why lambda based design rules are adopted across the industry.

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Bob

bobn2
bobn2 Forum Pro • Posts: 69,811
Re: Read Noise from DXOmark "Full SNR" data . 2

DSPographer wrote:

Both pixel size and pixel noise have tended to decrease with time. Now bobn2 has suggested this is a cause and effect relationship resulting from his scaling law.

Please stop misrepresenting what I say. If you want to discuss this sensibly, stop putting up straw men.

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Bob

bobn2
bobn2 Forum Pro • Posts: 69,811
Answering Joe's question from the last thread.

Great Bustard wrote:

bobn2 wrote:

Remember that what you see is only what the camera lets you see. If cameras have a base ISO of 100, similar QE, then the saturation capacity will be what similar, give or take manufacturers allowing different amounts of headroom. So that is self fulfilling. You don't know what would be the actual 'full well' (as is, the potential wells are 'full' of any sensor, only what is the largest allowed input to the ADC at the lowest allowed ISO setting.

are you saying that, for example, it's entirely possible that a pixel from the EM5 sensor can absorb the same amount of light as a pixel from the Canon 6D sensor, but the ADC is holding it back from an ISO 25 setting, in an analogous manner that Canon's ADCs limit the DR at lower ISOs?

It's very unlikely that the pixel from an EM5 can absorb the same amount as light as a 6D sensor, since it's got a quarter of the area. What is quite possible though is what you see as 'base ISO' has no relation to the absolute charge capacity of the sensor's pixels. Raw file results only show what happens at the end of the capture chain, not the absolute capability of the pixel design. It's important not to be misled by the term 'full well capacity'. This terminology relates to CCDs, where the charge was held in place by a potential well, maintained by a voltage on an electrode, and moved to shift the charge to the read transistor. CMOS sensors don't have 'wells' in the same way. Pinned photodiodes are rather shallow pools. The 'well' that in the end determines the absolute charge capacity is the floating diffusion which collects the charge on readout.

Still, what generally determines the operating maximum charge is downstream concerns, the voltage swing of the SF transistor or sometimes the input swing of the ADC. As it says in the Aptina white paper :

Generally, the amount of voltage swing allowed in the pixel is fixed by the overall sensor design. This fixed range of voltage means that CG can have a distinct impact on the sensor’s FW. For example, in a typical design, the power supply is fixed at 2.8 V and the analog signal chain has a fixed window of 1 V allowed voltage swing at the input. For example, if 1 V of swing is allowed at the pixel’s output and the source follower (SF) gain is 0.8, then the allowed voltage swing at the FD is equal to 1 V / 0.8 = 1.25 V. As shown above, the capacitance of the FD node will determine the amount of charge that can be detected within the fixed voltage operating range.

the impact of this is that the so called 'FWC' is just as likely to be a 'full ADC capacity', that is that the absolute charge capacity of the pixel may not be one of the designers absolute design goals. Or, think of it another way, if the same FD/SF was used for an 18MP FF and an 18MP APS-C sensor design, the result would be that at the same exposure, the FF design would produce 2.65 times higher voltage output than the FF design due to the larger light collection area. This can be simply compensated by using 2.65 times more voltage gain for the APS-C sensor. If this is what sensor designers were doing, you'd expect, for instance, a Canon 18MP FF sensor to have about 2.65 times the read noise at base ISO as would a Canon 18MP APS-C sensor.

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Bob

Eric Fossum
Eric Fossum Senior Member • Posts: 1,553
Re: Read Noise vs Pixel Pitch
7

bobn2 wrote:

I really don't want to get back into the same pretty pointless exchange that want on in the last thread, but I think this post is a pretty one-sided representation of the discussion. I'm just going to annotate it to put my side and then be done.

DSPographer wrote:

The thread also took a side track in a discussion about normalizing read noise per sensor area when bobn2 posted the following scaling law:

"I think that input referred read noise, that is expressed in 'electrons' is fundamentally affected by the 'gain' (charge/voltage factor) which in turn is controlled by the capacitance of the SF and floating diffusion.

That in turn is controlled by the area.

If you meant PIXEL area, then this last sentence is definitely not correct.  If you meant FD area, then you are partially correct since it also depends on 3D effects and what the FD doping is.  Generally the effective per-unit-area cap of the FD is increased during scaling so it is not strictly controlled by its area.  Likewise, the things the FD is connected to also contribute to its capacitance (RST and SF transistors) and they also do not scale in a straight forward way (e.g. the oxide thickness is also scaled).

So, if we want to isolate the effect of one variable (there are of course many) then we need to look at how things change if you change just that variable. So if you use the same process, same design and simply do a uniform geometrical scale than the capacitance of the read node will fall proportional to area, and so will the read noise."

And this is an effect that no-one has mounted any argument against.

Untrue. I feel like no one is listening.  I did in the original thread and have again here. See above.

So, we have a clear effect that if you make the SF/FD smaller

You mean the capacitance of that node, which may not be much smaller if the FWC is about the same due to other process and design considerations to counteract the area scaling affect on FWC.  Not CLEAR.

, the conversion gain will rise and the input referred noise for a given voltage noise. The question is, if you change the size of the SF/FD, does the voltage noise change and if so, does it change by enough to cancel out this effect.

He then added this caveat:
"Now of course, there are many more variables, and designers don't make pixels smaller simply by scaling, and in some cases are constrained by process limits"

While designers do not simply make pixels smaller by scaling, it seems a fair assumption that smaller SF/FD will be used as pixels shrink.

You mean plan-view area, but I think you are equating that to capacitance.

The 'uniform scaling' model simply models that.

which would thus be incorrect.

We don't know in practice whether instead of shrinking the active parts of the pixel, some designers are willing to sacrifice fill factor, or a bit of both. Nonetheless, we might expect smaller pixels to result in smaller components and thus be subject to the effect above, to some degree.

Yes

I have also added the caveat that there are noises which will increase as the transistor is reduced in size. Leaving that out allows my position to be characterised as saying that the CG effect is the only one in operation. That is a mischaracterisation of what I have said.

It seems like it was what you were saying early on but glad we agree at least now.

But he then goes on to imply this is the reason for the improvements in read noise:
"(though for those that claim that they must always use design rules on process limits, it's notable that Canon made a three-fold reduction in pixel area, while reducing read noise (co-incidentally, three fold) and increasing QE, using the same 500nm process)."

It's asking the question of people who believe component size must always be driven by process limits. Canon has shrunk pixels by a factor of three, while increasing QE and using the same process limits. I think its hard to conceive how they did that without shrinking components, in which case the original designs cannot have been close to process limits.

Now bobn2 and I had discussed this before. The issue was not that we disagreed about what happens for a given scaling rule, it was which scaling rule was relevant when discussing how read noise varies with pixel size. He felt the law above was most relevant; and I felt that for a given generation designers would be most likely to use a minimum effective gate length for the critical SF transistor based on process capability (note that improvements in effective gate length are still possible within a single process as it matures), and vary the gate width to achieve the FD capacitance needed for the desired full well capacity. Using arguments based on transistor thermal noise bob's model suggests that read noise should scale by pixel area, and my model suggests read noise could be independent of area.

See above.

Which is right? It turns out that it seems that neither model is very relevant. First, the assumption that simple thermal noise dominates read noise is not valid; and secondly, the most important factors in pixel read noise may not be included in our simplistic models.

However, the conversion gain effect must operate. The question is not whether it has an effect, but what other effects confound it, and to what end effect.

We are fortunate that someone actually involved in reducing read noise in image sensors, Eric Fossum, contributed to the thread. He listed the factors involved in reducing read noise:

"I think I have written this before but the read noise of the pixel in the case of correlated double sampling (CDS), depends on size of the main readout transistor. Smaller = noisier, in general. The noise is often limited by random-telegraph signal (RTS) noise which is thought to be a major contributor to 1/f noise. When possible, we make the main readout transistor as large as possible without compromising pixel fill factor.

The real question here is whether eric is referring to input referred or voltage noise. This isn't clear. I think the above must be true in terms of voltage noise, smaller transistors will be noiser. The question is still whether or not it frustrates

So, based on this we would expect an increase in read noise as we shrink pixels. Image sensor technologists have tried to reverse this by several techniques.

1. BSI - one benefit of BSI is more room for the readout electronics and that key transistor.

Clearly, when we compare DSLR sensors BSI is not an effect

only today.

, so we can ignore that as and explanation for the noise reduction in the sensors.

2. More attention to reducing the defects that contribute to RTS and hence reduce the noise of the transistor, or by burying the channel so surface defects don't contribute.

Certainly.

3. Increasing the conversion gain of the output node (volts/electron = 1/capacitance) so the input-referred noise appears to drop, even if the voltage noise increases. This is the standard EE approach - add gain as early as possible in the signal chain. Increasing the conversion gain is possible because FWC has dropped so there is often less charge to accomodate on the output node. Smaller technology also helps make the output node smaller and have less capacitance.

This is exactly the effect that I have posited above. (my emboldening)

Yes, my operative word is "helps"  True, except when people intentionally optimize and design the device differently.  It depends on what is going on with the FWC and several other trades that marketing people and camera makers prefer.  They all have different ideas about what is important.

4. Improving CDS, for example by digital CDS, so that any residual correlated noise is further reduced.

Improved CDS will help reset noise.

Yes, but you need to think through the components of reset noise.  There are many.

Probably there are one or two other things I have forgotten for the moment. The bottom line is that the result of these measures is a net DECREASE in read noise down to the 1-5 e- rms level. It has been a lot of hard work to reduce the read noise. (and another big effort in increasing FWC which is more or less a separate endeavor except for conversion gain). But if one were to plot read noise as a function of pixel size, as you guys like to do, you will see the outcome of this war on read noise. But, don't get fooled into thinking read noise seems to be scaling with pixel area due to any fundamental or natural technological reason."

Dr. Fossum also summarized how the reduction of read noise relates to a uniform pixel shrink:

"So, the recap the recap, the downward read noise trend is the result of hard work and new innovation, and NOT the natural result of scaling everything with area. You cannot just shrink the pixel this way. If it was, life would be a lot easier. As I have said several times, creating a predictive trend model is fine, but does not reflect cause and effect."

Which is arguing against something that I never said. I have never said that smaller pixels are designed simply by scaling bigger ones, simply that as an abstraction of the process of shrinking pixels, scaling is the most sensible one, because it models the fact that as pixels reduce in size the internal components of a pixel will be reduced in size, which they will be, if fill factor is not to suffer.

Bob, you are still thinking plan view, and not in 3D with doping and oxide and design parameter changes in mind.  If you simplify this to this level, it might make you feel like you understand what is going on but things are more complicated then this in real life. But yes, if I was teaching a beginning course then I too would talk about many of the same simple ideas because they are easier to understand.  Someone once said "advanced classes are about telling fewer lies"

Note that the capacitance reduction effect, and resultant rise in CG is definitely one of the factors which Eric says mitigate the rise and result in a 'net DECREASE in read noise' (his words, not mine). I hope at least I can continue to say that the rise in CG due to the reduction in component size is one of the factors which has contributed to the decrease, which is all my case amounts to, and which Eric confirms.

Yes, you are correct here, if you change it to "due in part to the reduction..."

PS: A scaling rule based on 1/f noise instead of thermal noise was also posted to the thread. I personally doubt that this is very useful for predicting how pixel noise would change as a pixel is shrunk. The reason is that the formula includes a process dependent factor. My understanding is that factor could greatly change as a new process is created to allow smaller pixels.

If we try to isolate the effect of one factor, we assume all other factors remain constant. that is the usual engineering practice. The process dependent constant (and there is another different one in the RTS equations) simply would give process dependent constants in any expression derived for the effects of scaling. That's not a bad thing. And the concept of scaling is fundamental to LSI design, that is why lambda based design rules are adopted across the industry.

No, this is old.  Lambda design rules are DEAD.  They were a simple concept (ala Mead and Conway) but have not been used in 20 years, if at all, in industry. Too simple, but easy to understand.

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Bob

Bob, the message from me is "oversimplification can lead to false conclusions".  So, you have presented a fine understanding of pixel design at the beginner level.  But, because it is more complicated than what you present, some of your statements are erroneous.  Also, remember I jumped into the discussion when someone tried to normalize read noise by area, as if it was a physical relationship, which it is not.

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DSPographer Senior Member • Posts: 2,483
Re: Read Noise vs Pixel Pitch

Eric Fossum wrote:
Also, remember I jumped into the discussion when someone tried to normalize read noise by area, as if it was a physical relationship, which it is not.

We should make clear that we normalize by area *not* because it makes sense as a physical relationship, but instead to give information (along with QE) on what the low light noise performance impact would be if the size of the pixels on a sensor was changed.

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bobn2
bobn2 Forum Pro • Posts: 69,811
Re: Read Noise vs Pixel Pitch

Eric Fossum wrote:

bobn2 wrote:

I really don't want to get back into the same pretty pointless exchange that want on in the last thread, but I think this post is a pretty one-sided representation of the discussion. I'm just going to annotate it to put my side and then be done.

DSPographer wrote:

The thread also took a side track in a discussion about normalizing read noise per sensor area when bobn2 posted the following scaling law:

"I think that input referred read noise, that is expressed in 'electrons' is fundamentally affected by the 'gain' (charge/voltage factor) which in turn is controlled by the capacitance of the SF and floating diffusion.

That in turn is controlled by the area.

If you meant PIXEL area, then this last sentence is definitely not correct. If you meant FD area, then you are partially correct since it also depends on 3D effects and what the FD doping is. Generally the effective per-unit-area cap of the FD is increased during scaling so it is not strictly controlled by its area. Likewise, the things the FD is connected to also contribute to its capacitance (RST and SF transistors) and they also do not scale in a straight forward way (e.g. the oxide thickness is also scaled).

So, if we want to isolate the effect of one variable (there are of course many) then we need to look at how things change if you change just that variable. So if you use the same process, same design and simply do a uniform geometrical scale than the capacitance of the read node will fall proportional to area, and so will the read noise."

And this is an effect that no-one has mounted any argument against.

Untrue. I feel like no one is listening. I did in the original thread and have again here. See above.

So, we have a clear effect that if you make the SF/FD smaller

You mean the capacitance of that node, which may not be much smaller if the FWC is about the same due to other process and design considerations to counteract the area scaling affect on FWC. Not CLEAR.

, the conversion gain will rise and the input referred noise for a given voltage noise. The question is, if you change the size of the SF/FD, does the voltage noise change and if so, does it change by enough to cancel out this effect.

He then added this caveat:
"Now of course, there are many more variables, and designers don't make pixels smaller simply by scaling, and in some cases are constrained by process limits"

While designers do not simply make pixels smaller by scaling, it seems a fair assumption that smaller SF/FD will be used as pixels shrink.

You mean plan-view area, but I think you are equating that to capacitance.

The 'uniform scaling' model simply models that.

which would thus be incorrect.

We don't know in practice whether instead of shrinking the active parts of the pixel, some designers are willing to sacrifice fill factor, or a bit of both. Nonetheless, we might expect smaller pixels to result in smaller components and thus be subject to the effect above, to some degree.

Yes

I have also added the caveat that there are noises which will increase as the transistor is reduced in size. Leaving that out allows my position to be characterised as saying that the CG effect is the only one in operation. That is a mischaracterisation of what I have said.

It seems like it was what you were saying early on but glad we agree at least now.

But he then goes on to imply this is the reason for the improvements in read noise:
"(though for those that claim that they must always use design rules on process limits, it's notable that Canon made a three-fold reduction in pixel area, while reducing read noise (co-incidentally, three fold) and increasing QE, using the same 500nm process)."

It's asking the question of people who believe component size must always be driven by process limits. Canon has shrunk pixels by a factor of three, while increasing QE and using the same process limits. I think its hard to conceive how they did that without shrinking components, in which case the original designs cannot have been close to process limits.

Now bobn2 and I had discussed this before. The issue was not that we disagreed about what happens for a given scaling rule, it was which scaling rule was relevant when discussing how read noise varies with pixel size. He felt the law above was most relevant; and I felt that for a given generation designers would be most likely to use a minimum effective gate length for the critical SF transistor based on process capability (note that improvements in effective gate length are still possible within a single process as it matures), and vary the gate width to achieve the FD capacitance needed for the desired full well capacity. Using arguments based on transistor thermal noise bob's model suggests that read noise should scale by pixel area, and my model suggests read noise could be independent of area.

See above.

Which is right? It turns out that it seems that neither model is very relevant. First, the assumption that simple thermal noise dominates read noise is not valid; and secondly, the most important factors in pixel read noise may not be included in our simplistic models.

However, the conversion gain effect must operate. The question is not whether it has an effect, but what other effects confound it, and to what end effect.

We are fortunate that someone actually involved in reducing read noise in image sensors, Eric Fossum, contributed to the thread. He listed the factors involved in reducing read noise:

"I think I have written this before but the read noise of the pixel in the case of correlated double sampling (CDS), depends on size of the main readout transistor. Smaller = noisier, in general. The noise is often limited by random-telegraph signal (RTS) noise which is thought to be a major contributor to 1/f noise. When possible, we make the main readout transistor as large as possible without compromising pixel fill factor.

The real question here is whether eric is referring to input referred or voltage noise. This isn't clear. I think the above must be true in terms of voltage noise, smaller transistors will be noiser. The question is still whether or not it frustrates

So, based on this we would expect an increase in read noise as we shrink pixels. Image sensor technologists have tried to reverse this by several techniques.

1. BSI - one benefit of BSI is more room for the readout electronics and that key transistor.

Clearly, when we compare DSLR sensors BSI is not an effect

only today.

, so we can ignore that as and explanation for the noise reduction in the sensors.

2. More attention to reducing the defects that contribute to RTS and hence reduce the noise of the transistor, or by burying the channel so surface defects don't contribute.

Certainly.

3. Increasing the conversion gain of the output node (volts/electron = 1/capacitance) so the input-referred noise appears to drop, even if the voltage noise increases. This is the standard EE approach - add gain as early as possible in the signal chain. Increasing the conversion gain is possible because FWC has dropped so there is often less charge to accomodate on the output node. Smaller technology also helps make the output node smaller and have less capacitance.

This is exactly the effect that I have posited above. (my emboldening)

Yes, my operative word is "helps" True, except when people intentionally optimize and design the device differently. It depends on what is going on with the FWC and several other trades that marketing people and camera makers prefer. They all have different ideas about what is important.

4. Improving CDS, for example by digital CDS, so that any residual correlated noise is further reduced.

Improved CDS will help reset noise.

Yes, but you need to think through the components of reset noise. There are many.

Probably there are one or two other things I have forgotten for the moment. The bottom line is that the result of these measures is a net DECREASE in read noise down to the 1-5 e- rms level. It has been a lot of hard work to reduce the read noise. (and another big effort in increasing FWC which is more or less a separate endeavor except for conversion gain). But if one were to plot read noise as a function of pixel size, as you guys like to do, you will see the outcome of this war on read noise. But, don't get fooled into thinking read noise seems to be scaling with pixel area due to any fundamental or natural technological reason."

Dr. Fossum also summarized how the reduction of read noise relates to a uniform pixel shrink:

"So, the recap the recap, the downward read noise trend is the result of hard work and new innovation, and NOT the natural result of scaling everything with area. You cannot just shrink the pixel this way. If it was, life would be a lot easier. As I have said several times, creating a predictive trend model is fine, but does not reflect cause and effect."

Which is arguing against something that I never said. I have never said that smaller pixels are designed simply by scaling bigger ones, simply that as an abstraction of the process of shrinking pixels, scaling is the most sensible one, because it models the fact that as pixels reduce in size the internal components of a pixel will be reduced in size, which they will be, if fill factor is not to suffer.

Bob, you are still thinking plan view, and not in 3D with doping and oxide and design parameter changes in mind. If you simplify this to this level, it might make you feel like you understand what is going on but things are more complicated then this in real life. But yes, if I was teaching a beginning course then I too would talk about many of the same simple ideas because they are easier to understand. Someone once said "advanced classes are about telling fewer lies"

Note that the capacitance reduction effect, and resultant rise in CG is definitely one of the factors which Eric says mitigate the rise and result in a 'net DECREASE in read noise' (his words, not mine). I hope at least I can continue to say that the rise in CG due to the reduction in component size is one of the factors which has contributed to the decrease, which is all my case amounts to, and which Eric confirms.

Yes, you are correct here, if you change it to "due in part to the reduction..."

PS: A scaling rule based on 1/f noise instead of thermal noise was also posted to the thread. I personally doubt that this is very useful for predicting how pixel noise would change as a pixel is shrunk. The reason is that the formula includes a process dependent factor. My understanding is that factor could greatly change as a new process is created to allow smaller pixels.

If we try to isolate the effect of one factor, we assume all other factors remain constant. that is the usual engineering practice. The process dependent constant (and there is another different one in the RTS equations) simply would give process dependent constants in any expression derived for the effects of scaling. That's not a bad thing. And the concept of scaling is fundamental to LSI design, that is why lambda based design rules are adopted across the industry.

No, this is old. Lambda design rules are DEAD. They were a simple concept (ala Mead and Conway) but have not been used in 20 years, if at all, in industry. Too simple, but easy to understand.

Bob, the message from me is "oversimplification can lead to false conclusions". So, you have presented a fine understanding of pixel design at the beginner level. But, because it is more complicated than what you present, some of your statements are erroneous. Also, remember I jumped into the discussion when someone tried to normalize read noise by area, as if it was a physical relationship, which it is not.

Hi Eric,

I think we are talking once again at cross purposes. Let's try to characterise my position again. I don't say that real designers design pixels by just scaling. I don't say that the area scaling of the CG is the only effect in operation. Let's just take this bit one at a time. Here's a number of questions, just to tease out which of my statements are 'erroneous'.

As a general rule, do sensor designers try to make the SF as big as possible?

If the answer to that is 'yes', is 'as big as possible' going to be smaller in a small pixel than a big pixel? (again, in general).

Is it the case in general that smaller pixels will use processes which make capacitance of the FD per unit area larger than for large pixels?

Let's start with those, and see where we go.

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Bob

Steen Bay Veteran Member • Posts: 7,418
Pixel size, read noise and DR
1

Mikael Risedal wrote:

Conclusion?

Now when the storm seems to have subsided, did you come to any conclusion ?

Not sure, but if the conclusion was that the best small pixels and the best larger pixels as a general rule will have about the same read noise (e-), then that means that sensors with larger pixels will have an advantage in normalized DR ('print'/8mp). If the read noise is constant regardless of the pixel size and ISO, then a 64mp FF sensor will have 1 Ev/stop less normalized DR than a 16mp FF sensor at all ISOs, and a 256mp sensor will have 2 stops less normalized DR (assuming same QE).

If so, then more MPs (higher resolution) won't be a free lunch. It'll come at the cost of reduced DR, which could be a problem at especially high ISOs where the DR ain't that high to start with.

Iliah Borg Forum Pro • Posts: 28,882
Re: Read Noise vs Pixel Pitch
1

At some point Zeiss salespeople, and especially those who worked with Hasselblad lenses, were very much against using resolution per mm as a system charactheristic. They insisted on resolving distant black objects over the bright background. "See that small hump on the electric wires? It is a bird sitting there! You can't see it with any other lenses but Zeiss." But using an enlarger we need to know how far we can go, so it eventually came to lppmm/lppi, and next to MTF. And noise affects resolution too, so for a person who is to decide on the print size such a measure is of interest.

bobn2
bobn2 Forum Pro • Posts: 69,811
Re: Read Noise from DXOmark "Full SNR" data . 2

DSPographer wrote:

you can generate a curve that goes *exactly* through all points on the plot (to double precision accuracy)

You don't find that odd?

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Bob

Eric Fossum
Eric Fossum Senior Member • Posts: 1,553
Re: Read Noise vs Pixel Pitch
6

Hi Eric,

I think we are talking once again at cross purposes. Let's try to characterise my position again. I don't say that real designers design pixels by just scaling. I don't say that the area scaling of the CG is the only effect in operation. Let's just take this bit one at a time. Here's a number of questions, just to tease out which of my statements are 'erroneous'.

I thought I was very specific about which statements were erroneous, but.....carry on.

As a general rule, do sensor designers try to make the SF as big as possible?

Not as a general rule.

If the answer to that is 'yes', is 'as big as possible' going to be smaller in a small pixel than a big pixel? (again, in general).

Is it the case in general that smaller pixels will use processes which make capacitance of the FD per unit area larger than for large pixels?

"Per unit area" is not a good measure for such small dimensions due to 3D effects, and the strong impact of stray capacitance and other components connected to the actual FD, but aside from that, yes, the p-doping under the n+ implant is usually adjusted upward.

Again, you are trying to simplify the model of the FD as a plate capacitor whose area is smaller and whose plate spacing is also smaller.  It isn't really so simple at all.  In fact, it is so complicated that the actual capacitance is just numerically extracted from the layout and process sim in software.  Hand estimates will get you within a factor of 2 or 3, which is not close enough.

C = dQ/dV and Q=Q(V) so the voltage dependence is also a factor and contributes non-linearity.

In a plate capacitor C = Q/V to a good approximation and life is easy.

Let's start with those, and see where we go.

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Bob

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Mikael Risedal
OP Mikael Risedal Veteran Member • Posts: 4,644
Re: Pixel size, read noise and DR

Steen Bay wrote:

Mikael Risedal wrote:

Conclusion?

Now when the storm seems to have subsided, did you come to any conclusion ?

Not sure, but if the conclusion was that the best small pixels and the best larger pixels as a general rule will have about the same read noise (e-), then that means that sensors with larger pixels will have an advantage in normalized DR ('print'/8mp). If the read noise is constant regardless of the pixel size and ISO, then a 64mp FF sensor will have 1 Ev/stop less normalized DR than a 16mp FF sensor at all ISOs, and a 256mp sensor will have 2 stops less normalized DR (assuming same QE).

If so, then more MPs (higher resolution) won't be a free lunch. It'll come at the cost of reduced DR, which could be a problem at especially high ISOs where the DR ain't that high to start with.

then why have not canon (as one example) reduced the read-out noise in any of their sensors with a larger pixel area? and increased theirs DR?

My view is that a smaller pixel generate less noise than a bigger one

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bobn2
bobn2 Forum Pro • Posts: 69,811
Re: Read Noise vs Pixel Pitch
3

Eric Fossum wrote:

Hi Eric,

I think we are talking once again at cross purposes. Let's try to characterise my position again. I don't say that real designers design pixels by just scaling. I don't say that the area scaling of the CG is the only effect in operation. Let's just take this bit one at a time. Here's a number of questions, just to tease out which of my statements are 'erroneous'.

I thought I was very specific about which statements were erroneous, but.....carry on.

This is perhaps why we keep on going at cross purposes. I read most of your critique as being 'a simplification and there are other important factors', not 'erroneous'. So far, no-one seems to me to have said that anything that I have said is wrong, just that it's a simplification. Of course it is, I know that. We deal with such simplifications in engineering all the time. What

As a general rule, do sensor designers try to make the SF as big as possible?

Not as a general rule.

Good, that co-incides with my observation.

If the answer to that is 'yes', is 'as big as possible' going to be smaller in a small pixel than a big pixel? (again, in general).

Is it the case in general that smaller pixels will use processes which make capacitance of the FD per unit area larger than for large pixels?

"Per unit area" is not a good measure for such small dimensions due to 3D effects, and the strong impact of stray capacitance and other components connected to the actual FD, but aside from that, yes, the p-doping under the n+ implant is usually adjusted upward.

Again, you are trying to simplify the model of the FD as a plate capacitor whose area is smaller and whose plate spacing is also smaller. It isn't really so simple at all. In fact, it is so complicated that the actual capacitance is just numerically extracted from the layout and process sim in software. Hand estimates will get you within a factor of 2 or 3, which is not close enough.

C = dQ/dV and Q=Q(V) so the voltage dependence is also a factor and contributes non-linearity.

In a plate capacitor C = Q/V to a good approximation and life is easy.

Certainly, I'm not remotely thinking that anyone would try to design a sensor using these gross simplifications. Again, the same is true of most engineering abstractions, they are real simplifications of the actual situation. That doesn't make them 'erroneous'. I have a colleague who works on concrete structures. They have basic equations which describe the way that the strength of a beam will change with the size. Of course these are gross simplifications, because the strength of the concrete depends on things like distribution of the aggregate and the curing process, which in turn depends on things like the amount of water in the mix. In the case of poured concrete construction these are very difficult to determine accurately, and so real design methods much more complex than the simplification will dictate.

I think the basic problem between you and I here is that you are treating this 'model' as an absolute predictive design model. Obviously it isn't and was never intended to be. It is in the context of the long, long debate on these forums, where many want to say as an absolute rule that smaller pixels will result in 'more noise' or 'lower DR' at an image level. You and I know absolutely that is not the case. You observed yourself that on the whole designers have managed to reduce read noise as pixels have shrunk. You yourself observed that one of the contributors to that is the increase in CG and also that a reduction in area also contributes something towards that increase in CG (even if, once again it is not the whole story). So, my discussion of the relationship of CG to capacitance and the relationship between CG and read noise should be taking simply as an attempt to introduce those that were unaware that there is a fundamental effect that will help smaller pixels have a lower read noise, not that it is the only contributor nor that this reduction is automatic. Before I introduced it mostly people here were unaware of the role of CG in read noise or the relationship of CG to capacitance. That is only what it is about. No way is it an attempt on my part to introduce a new theory on sensor design. The way you and DSP have gone at it, I feel that you must have interpreted it that way. If I was trying to do that, I reckon I would have published elsewhere.

However, having said that, we can find ranges of sensors where the CG must be playing an important part in read noise reduction - the canon ones come to mined. Noe of those is BSI, so we can rule that one out, Canon appears not to have substantially changed the CDS methods, so we can rule that out. Possibly they have moved to buried channel and the like, but I strongly suspect that CG has been the biggest factor in the three fold read noise reductio that they have achieved, and their read noise figures strongly suggest that all their sensors of a generation have about the same CG, whatever the pixel size. Now, given that for many years Canon was pushing the pixel increase agenda, it's not unreasonable I think to speculate that the CG gain was driven by the reduction in pixel size and then applied to larger pixels, rather than the other way round. Perhaps that biggest giveaway was the co-relase of the 50D which pushed the pixel count to 15MP and the 5DII, which had the same pixel count as the 1DsIII. Both cameras had about the same read noise, which was an improvement over the 1DsIII. Not perhaps too big a stretch of the imagination to think that the 50D circuitry was transplanted in the 1DsIII pixel (there were obviously other differences to cater for video on the 5DII).

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Bob

Steen Bay Veteran Member • Posts: 7,418
Re: Pixel size, read noise and DR

Mikael Risedal wrote:

Steen Bay wrote:

Mikael Risedal wrote:

Conclusion?

Now when the storm seems to have subsided, did you come to any conclusion ?

Not sure, but if the conclusion was that the best small pixels and the best larger pixels as a general rule will have about the same read noise (e-), then that means that sensors with larger pixels will have an advantage in normalized DR ('print'/8mp). If the read noise is constant regardless of the pixel size and ISO, then a 64mp FF sensor will have 1 Ev/stop less normalized DR than a 16mp FF sensor at all ISOs, and a 256mp sensor will have 2 stops less normalized DR (assuming same QE).

If so, then more MPs (higher resolution) won't be a free lunch. It'll come at the cost of reduced DR, which could be a problem at especially high ISOs where the DR ain't that high to start with.

then why have not canon (as one example) reduced the read-out noise in any of their sensors with a larger pixel area? and increased theirs DR?

They have. Cameras like the 6D and 1Dx have less than 2 e- read noise at the highest ISOs, according to DSPographer :

http://www.dpreview.com/forums/post/52422014

..and it seems that the best BSI sensors with small pixels (like SX50, S120 and RX 100 II) can't quite match that.

My view is that a smaller pixel generate less noise than a bigger one

Smaller pixels need to have a lower read noise than larger pixels in order to maintain the same normalized DR on a given sensor size, because the read noise will increase by the linear scaling factor when normalizing/downsampling to the same output size (like DxO's print/8mp figures). For example, if a 16mp FF sensor has 2 e- read noise, then the read noise on a 64mp FF sensor must be 1 e-, because the read noise will double from 1 e- to 2 e- if downsampling the 64mp image to 16mp.

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