D4 sensor derived from aptina technology

Started Oct 5, 2012 | Discussions thread
OP chn_andy Junior Member • Posts: 47
Update: Pixel binning a better clue?

chn_andy wrote:

Several months ago there has been a discussion on the read noise and full well capacity of D4 sensor when the camera is release. Now Chipworks finishes their teardown report on the sensor. Even though its unaffordable to people outside the IC design field like us, they are still generous enough to provide a Topic of Content for free, which provide adequate information on the pixel structure of the sensor.

People has been speculating in that discussion on the discrepancy of base ISO in video and photographic mode, given a ISO200 in video. Now here's the definitive answer: D4 sensor seems to adopt the Aptina DR-Pix technology!

In the TOC, it has shown that 2 pixels share a single floating diffusion (FD) node, with 2 transfer gates, 1 reset, 1 source follower and 1 row select. But, there's an additional one called: Floating Diffusion Switch Transistor, which I interpret as the DCG in Aptina Dr-Pix technology. Basically when this is switched on, the FD would connect to a capacitor, allow more charged to be measured at the same voltage range. And as a result, FWC is increased and allow ISO 100 to hold more than 100k electrons.

Previous D3s and D3 used 4 transistor in a single pixel.

Speculation often leads to bigger surprises, Chipworks has now made a blog post:


And this T6 switch connects the Floating Diffusion (FD) of adjacent columns! As Chipworks speculates, it might serve to offer analog pixel binning (Charge domain binning like CCD) to reduce aliasing and boost ISO in full FOV video. Meanwhile, this switch can also serve to increase charge capacity by offering twice as large FD as before to realize ISO 100.

How this can be done? I guess since Nikon did not adopt Sony's Exmor column parallel technique, adjacent FD can be combined to act more like a 4 pixel sharing instead of 2. Then readout the 4 pixels in a Bayer block sequentially. Since the readout speed is not defined by column timing but by pixel timing, it will only alter the output pixel order and pattern while not impeding the frame rate.

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