Fast lenses, and High ISO

Started 4 months ago | Discussions thread
bobn2
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Re: Understanding ISO
In reply to mosswings, 4 months ago

mosswings wrote:

Chikoo wrote:

Austinian wrote:

Great Bustard wrote:

The most important factors about the sensor that manufacturers do not tell us are:

  • QE (Quantum Efficiency -- the proportion of light falling on the sensor that is recorded)
  • Read Noise (the additional electronic noise added by the sensor and supporting hardware)
  • CFA (Color Filter Array)
  • Microlens Efficiency

Which of these are likely to see significant improvements in the fairly near term (next few years)?

If by significant you mean something that might garner an extra stop or more of performance, it's hard to say. There has been recent work by Panasonic on a different type of CFA that eliminates the losses inherent in current implementations and that theoretically could yield a stop, perhaps more, in sensitivity:

http://www.imaging-resource.com/news/2013/02/05/bye-bye-bayer-panasonic-claims-new-sensor-tech-ends-color-filter-light-loss

It's been over a year since this announcement, but no updates. One of the problems of this technique may lie in tailoring the color splitting response to produce acceptable color rendition. Given all the complaints about current CFAs, it will need to be no worse.

BSI (backside illumination) is the current go-to for increasing sensor QE. Sony calls it EXMOR-R and it is found on no larger than 1" sensors as it involves thinning the sensor wafer down to a few 10s of microns in order to expose the pixel wells from the backside. Doing this for a larger format sensor is still impractical as it dramatically weakens the chip.

Sony's trying to curve their sensor to eliminate corner vignetting and the need for tricky microlens tailoring. It also has the side effect of improving sensor response by straining the sensor lattice, but again it's an expensive technique.

Read noise can be attacked in several ways, but another way of dealing with the problem may be in redefining the entire imaging process. This is what Eric Fossum has been working on with his Quanta Imaging Sensor. It basic trades the charge-integrating approach of today for a photon-counting approach using a combination of extremely dense binary-response pixel arrays, high frame capture rates, and heavy postprocessing - 100+MP arrays, 1000 frames/sec capture rates using fairly conventional CMOS technology. In doing so one can trade off resolution for DR, tailor tonal response directly, possibly directly compensate for camera motion, etc. etc.. The downside is that it requires pixel read noise to be about 4 stops better, but since it's not trying to do a linear amplification, more options for doing so are open to the designer. Research chips are in development now, but we have a long road to go.

Use a transparent wafer for BSI?

For electronic and manufacturing reasons you have to start with silicon, which isn't. But beyond that, you have to clear away all the wiring and other structures to gain QE, which is what BSI does - it flips the chip over where there isn't any wiring. The flipped wafer can then be cemented to a carrier substrate - a ceramic carrier, or something like that - and the back of the wafer ground down to the required thickness. A lot of today's ICs include what amounts to a pass with a wet sander.

There are two processes for BSI. One grows silicon epitaxy over a transparent (sapphire) wafer and then builds the circuits in the silicon. The other is the process you describe. I suspect that wafer thinning by grinding, as you describe, is going to cause too much silicon damage for it to be used, I suspect it is done by etching, dry or wet.

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Bob

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