Pixel Size vs Sensor Efficiency

Started May 18, 2012 | Discussions thread
DSPographer
Senior MemberPosts: 2,214
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Re: You have ignored read-out speed
In reply to bobn2, Jul 13, 2012

bobn2 wrote:

DSPographer wrote:

It is not difficult to pipeline and parallelize the output of the row buffer and digitization such that R dominates the pixel read time. I have already assumed this has been done so that D has negligible impact on the read time. Then, the only way to speed up the read out to allow more rows in the same frame time is to: increase the SF bandwidth, or use parallel column lines. That is my point I made at the beginning.

The case is here that we've both allowed ourselves to let our preconceptions argue us up a blind alley. You are right, in that there is only one column line per pixel then the row time is determined entirely by the number of rows and the time to read all of them. However, the basic assumption that your model is based on is still wrong. I was very lazy in developing the argument as to why it's wrong and just recycled the right answer to a different question, but your premise is still wrong. Here is the real reason why.

This is a timing diagram from Sony showing the operation of the Exmor output circuitry

The key signal to look at here is Vsf, the column line signal, driven by the source follower. The signal ϕs gates on row of pixels onto the column line, and its length is essentially determined by the row read period. Your hypothesis is based on the idea that the frequency content to the signal driven by the SF (Vsf) is essentially determined by the row time ( ϕs ) but as you see, it isn't. Essentially, it is controlled by the sampling requirements of the ADC. As this graph shows, there is time for two full ADC conversions in the line read time. In the case of conventional channels, all that is required is for the reset and pixel signal to be gated to the ADC input, which is in itself a small fraction of the line read time. That time is essentially still controlled by the ADC conversion time, which is why it can be reduced if the ADC's run faster. They'd have to read very fast though for the bandwidth of the SF to begin to be controlled by the line read time.

Your diagram does show that for the Exmor sensor the SF output settling time, while significant, does not dominate the row read time. I had in mind a Canon type circuit with sample and holds to maximize the settling time fraction.

If I recall correctly, in the Canon architecture there is a sample and hold at each input to the second stage's differential amplifier of the row buffer. First the reset is sampled onto a capacitor at the negative input of the differential amplifier, then the reset+signal value is sampled onto the capacitor at the positive input. The amplifier output then shows the CDS result. By simply ping-ponging two sets of these row buffers, the differential output of an even row's CDS result is sent to the A-D converter while an odd row's reset and reset+signal values are being sampled into the input of the other row buffer. In this way the available settling time of the SF is maximized for a given row read period. A disadvantage compared to your Exmor diagram is that the sample and hold used for the reset and reset+signal values are different, so, the CDS cannot compensate for the difference between them.

By including the hold time of the reset and reset+signal values in the row read out, the Exmor design allows the CDS to completely avoid any difference between the signal paths of the two values. The hold time of the reset signal can also be much shorter than for the reset+signal value since its range is limited: so the A-D down ramp time needed is much shorter than for the up ramp.

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