EETimes:

Toshiba has developed a new IC package that's as thin as a piece of paper.

Just as chip-scale packaging (CSP) technology greatly reduced the two-dimensional IC packages, the company's so-called "Paper Thin Package" (PTP) will reduce 3-dimensional scale of packages to about one tenth the height of a conventional device.

Toshiba has plans to use the technology to make higher-capacity flash memory storage cards by next year, and claims it can open the door to new applications.

The ultra-thin packaging technology was the product of the company's research in fabricating 300-mm wafers. Thanks to that research, Toshiba was able to shave the thickness of an IC down to a mere 50-microns, or about 90 percent thinner than conventional devices.

"To increase chip mounting density, stacking is more efficient than tiling small chips like CSPs. But when many chips are stacked on a printed circuit board, it becomes thick and protruding. That's why we've developed a technology which makes each chip package very thin," said Kenji Takahashi, chief specialist of Packaging Engineering Department at Toshiba Manufacturing Engineering Center.

At the laboratory, Toshiba researchers have developed a 130-micron-thick package, which is almost one-tenth the thickness of a 1.27-mm TSOP (thin small out-line package). TSOPs are widely used today for memory devices.

A 130-micron package is thinner than the 0.2-mm-thick paper used for business cards and slightly thicker than copier paper, which is about 0.1-mm thick. A maximum of eight chips can be stacked using the new package, which would make it 1-mm in height.

"Stacking several chips can enable large capacity. In the case of memory, this technology offers the most advanced generation capacity using silicon of the previous generation," said Takahashi. "Technically the technology can be applied to logic chips, but the effect is remarkable when it is used for memory chips."

"The first target is to stack four flash memories in one SmartMedia card," said Takahashi. A SmartMedia card is 0.75-mm high and has a 0.5-mm opening that can accommodate one flash memory device. Using the new package, Takahashi's team has set out to stack four flash devices in the same opening. By the first half of next year, Toshiba plans to ship samples of a 1-Gbit SmartMedia card which uses four stacked 256-Mbit flash devices.

While the thinness has advantages in applications with space constraints, the new paper-thin packaged chips also has advantages with regards to package-level test and can make use of existing manufacturing lines prior to mounting. Toshiba officials pointed out that such manufacturing advantages are similar to those gained by moving to CSP.

For PTPs, it's essential to use thinner chips than are mass produced today. To reduce thickness, Toshiba researchers leveraged technology the company had developed for handling 300-mm wafers to make chips that are 50-microns thick, or about one-tenth thickness of conventional chips.

In a conventional wafer fabricating process, wafers are ground and then diced into chips. But because larger 300-mm wafers are more susceptible to cracking during processing, Toshiba researchers developed a way to avoid handling the thin 300-mm wafers after the grinding process by dicing the chips before grinding the wafers, which they call Dicing Before Grinding (DBG).

Using the DBG method, chips that are fabricated on a wafer are cut halfway depth on a wafer. Then it is ground from the backside until the cut is reached, at which point the chips automatically separate. This process eliminates the handling of very thin ground wafer as a whole. Takahashi said, "with this technology, chips even on a 300 mm wafer can be made as thin as 50 microns."

Before marketing the parts, Toshiba researchers are going to optimize the carrier tape structures and materials - encapsulant resin and metal wiring - and to complete reliability testing. Takahashi said that in the laboratory, they've already achieved high reliability.

Thinner slices of silicon devices will also enable new applications, Takahashi said. Solid silicon becomes flexible when it becomes as thin as 50 microns, hence the PTP chip itself has enough flexibility to bend. Takahashi showed examples of new potential applications: A PTP chip pasted on the surface of a round glass surface; another that is encapsulated into an IC card that is 25% slimmer than today's cards; and a mock-up postage stamp-form chip which has wireless antenna and a chip that can be pasted to almost any surface.