Sony announces development of 35mm CMOS sensor
Pre-PMA 2008: In a surprise move Sony today announced its entry into the rapidly-expanding 24x36mm imaging sensor market with its own 24.81 megapixel CMOS offering. Joining Canon and Nikon in the full-frame market, this new chip promises to output all pixels at 6.3 fps with lower noise than other designs of similar pixel-pitch thanks to its “Column-Parallel A/D Conversion Technique” whereby each column of photosites is given its own Analogue to Digital Converter. The ADCs themselves are 12-bit, flying in the face of current trends which are toward 14-bit devices but the combination of speed, dynamic range and sheer resolving power displayed by this sensor make it one to watch for when Sony puts into full production hopefully before the year is out.
Sony Develops 35mm full size CMOS Image Sensor with 24.81 Effective Mega pixel resolution and extremely high signal conversion speed for use in Digital SLR Cameras
~ All-pixel scan mode of 6.3 frame/s ~
Tokyo, Japan – Sony Corporation today announced the development of a 35mm full size (diagonal: 43.3mm / Type 2.7) 24.81 effective megapixel, ultra-high speed high image quality CMOS image sensor designed to meet the increasing requirement for rapid image capture and advanced picture quality within digital SLR cameras.
CMOS Image Sensor
In recent years, the demand for digital SLR cameras featuring high resolution and wide graduation ranges capable of capturing every detail of the subject matter has continued to increase, particularly among high-end amateur users. Additionally, the increasing user requirement to shoot from the same focal length and angle as 35mm film cameras using interchangeable lenses has led to significant interest in the development of 35mm, full size CMOS image sensors.
However, there are a number of technical challenges to developing full (large) size image sensors, such as the propagation delay caused by using extended power circuitry and signal lines, and the difficulty of maintaining uniform sensitivity and signal saturation across the surface of the screen.
Furthermore, because current semiconductor exposure systems are unable to cover the entire chip surface of 35mm full size CMOS image sensors, multiple exposures are required. This results in the difficulty of accurately controlling exposure variance and matching circuit patterns.
Advantages of this device
The newly developed CMOS image sensor combines unique circuit design technology with Sony's advanced fabrication expertise, including a system of joining multiple exposed patterns together and advanced planarization for minimizing fluctuation, to realize 35mm, full size, 24.81 effective megapixel resolution. Sony’s “Column-Parallel A/D Conversion Technique” also provides each column within the sensor with its own A/D converter, minimizing image degradation caused by the noise that arises during analog processing while at the same time delivering an extremely high signal conversion speed.
The enhanced image quality generated by the sensor’s 24.81 effective megapixel resolution, wide range of graduation expression achieved by its full size broad dynamic range, and the low noise, high resolution, ultra-responsive performance provided by Sony’s Column-Parallel A/D Conversion technique enable it to meet the ever-increasing requirements within high performance digital SLR cameras.
Sony will target for mass production of this CMOS image sensor within this year.
- High picture quality in 35mm full size image sensor with 24.81M effective pixels
- “Column-Parallel A/D Conversion method” achieves high S/N and high-speed imaging
- High-speed digital output （12 channel parallel LVDS output）
- CDS/PGA (24dB) Circuit （PGA: Programmable Gain Amplifier）
- 12bit-AD Converter on chip
- Diversified readout mode
- All-pixel scan mode 6.3 frame/s (12bit)
- Window readout
- Image size Diagonal width 43.3mm (Type 2.7)
- Total number of pixels 6236 (H) x 4124 (V) approx. 25.72M pixels
- Number of effective pixels 6104 (H) x 4064 (V) approx. 24.81M pixels
- Number of active pixels 6096 (H) x 4056 (V) approx. 24.73M pixels
- Chip size 41.0mm (H) x 31.9 mm (V)
- Unit cell size 5.94μm (H) x 5.94μm (V)